Expanding High Speed Transport Interface Hardware Method For Motherboard

ABSTRACT

An expanding high speed transport interface hardware method for motherboard is provided. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket. Besides, more design choices and opportunities are provided for the manufacturers of motherboard and peripheral.

FIELD OF INVENTION

This application is a continuation-in-part of previously filedapplication Ser. No. 11/165,631, filed on Jun. 23, 2006. The presentinvention relates to an expanding interface hardware method, andparticularly to an expanding high speed transport interface hardwaremethod for a motherboard.

BACKGROUND OF THE INVENTION DESCRIPTION OF THE RELATED ART

There are several methods to expand hardware for a motherboard. However,the main method uses protocol control information (PCI) or PCI-Expressbus slot in the motherboard for expanding hardware. In practice, the PCIbus serves as an interface between a motherboard and a PMC (PCImezzanine card) module. Since most of I/O functions can be realizedthrough the PCI interface. For example, a display card in a computer issuch mezzanine card with a displaying function, which may be insertedonto a connector connected to the PCI bus of the computer mother board.

On the other hand, the PMC providers may only provide PMCs compatiblewith the connectors provided by the motherboard so that the PMCs may beconnected to the PCI bus on the motherboard and function normally.Accordingly, the PMCs to be used may not be selected in theirspecifications with respect to a specific computer motherboard.

In addition, the motherboard with plural CPU structure requires light inweight and small in size, so the extra space where can be utilized inthe motherboard is quite limited. Also, if a customer requires only oneCPU, other CPU insertion areas will become idle. In the other words, itis a space resource waste.

SUMMARY OF THE INVENTION

In view of the aforementioned problems, the present invention isdirected to providing an expanding high speed transport interfacehardware method for a motherboard. To solving the technique problem forprior art, the present invention provides an interface for connectingwith PCI bus without through the connector of a motherboard. The presentinvention provides a method by using a second or a third CPU socket inthe motherboard with plural CPU structure to expand high speed transportinterface hardware.

To solve the above-mentioned problem, the present invention provides anexpanding high speed transport interface hardware method applied to amotherboard with plural CPU structure. Wherein, among the CPU sockets ofthe motherboard, a CPU bus with high speed transport interface isutilized for connecting each CPU socket.

The method includes the following steps. Firstly, a mezzanine card isprovided, and the mezzanine card has a pin grid array disposed on thebottom surface of the mezzanine card. Besides, the top surface of themezzanine card has a chip socket with high speed transport interface andthe chip socket is electrically connected with the pin grid array. Next,an expanding hardware with high speed transport interface is installedin the chip socket. And then the mezzanine card is inserted into an idleCPU socket to make the pin grid array electrically connect with the pinholes of the CPU socket, so that the pin holes of the CPU socket can beelectrically connected to the expanding hardware with high speedtransport interface through electrically connecting with the CPU bus.Finally, the motherboard is booted and activated. The motherboard willdetect the expanding hardware in the mezzanine card and set the CPU busas a data transmission path so as to add an applicable and new expandingbus interface in the motherboard.

In the above embodiment, the high speed transport interface includes ahyper transport bus interface.

In the above embodiment, the expanding hardware is a bridge chipset,especially an AMD 8131 chipset.

By the connecting mechanism of the present invention, a high speedtransport interface hardware can be added. The present invention can beapplied to a motherboard with plural CPU sockets. More specific, thepresent invention is better to be used in a motherboard having an idleCPU socket. Therefore, the idle CPU socket can be used to connect withthe mezzanine card of the present invention for expanding a high speedtransport interface hardware, so that every CPU socket in themotherboard can be fully utilized. Besides, the expanding hardware iselectrically connected to a CPU chip inserted in the motherboard and canbe controlled by the CPU chip, so that the inserted CPU chip can alsogenerate an expanding effect by the method of the present invention.

Through the high speed transport interface achieved by the CPU socket ofthe present invention, many different products may be produced by thismethod. Therefore, business opportunities are generated.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription given hereinbelow illustration only, and thus is notlimitative of the present invention, and wherein:

FIG. 1 is a schematic diagram showing a motherboard with plural CPUsockets equipped thereon of the present invention;

FIG. 2 is a schematic diagram showing a mezzanine card loaded with ahigh speed transport interface hardware according to a preferredembodiment of the present invention; and

FIG. 3 is a flowchart of expanding high speed transport interfacehardware method for a motherboard of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

As shown in FIGS. 1, 2, and 3, FIG. 1 is a schematic diagram showing amotherboard with plural CPU sockets equipped thereon of the presentinvention, FIG. 2 is a schematic diagram showing a mezzanine card loadedwith a high speed transport interface hardware according to a preferredembodiment of the present invention, and FIG. 3 is a flowchart ofexpanding high speed transport interface hardware method of the presentinvention.

The expanding high speed transport interface hardware method for amotherboard of the present invention is applied to a motherboard 10 withplural CPU structure. The motherboard also includes a first CPU socket11 and a second CPU socket 12. A CPU bus 13 with high speed transportinterface is used to connect the first CPU socket 11 and the second CPUsocket 12. The high speed transport interface may be a hyper transportbus interface. The method of the present invention comprises thefollowing steps. Firstly, a mezzanine card 20 is provided. The mezzaninecard 20 has a pin grid array 21 disposed on the bottom of the mezzaninecard 20. The number of contact pins of the pin grid array 21 is lessthen that of pin holes of the second CPU socket 12. In addition, the topsurface of the mezzanine card 20 has a chip socket 22 with high speedtransport interface, and the chip socket 22 is electrically connectedwith the pin grid array 21 (Step S10). Of cause, the required peripheralcircuit for matching the expanding hardware 23 inserted in the chipsocket 22 is disposed in the mezzanine card 20 in advance. Next, anexpanding hardware 23 with high speed transport interface is installedin the chip socket 22 (Step S20). Therefore, the expanding hardware 23and the peripheral circuit of the mezzanine card 20 can form anintegrated circuit. At this time the first CPU socket has inserted witha CPU chip, and then the mezzanine card 20 is inserted into an idlesecond CPU socket 12 to make the pin grid array 21 electrically connectwith the pin holes of the second CPU socket 12, so that the pin holes ofthe first CPU socket can be electrically connected with the expandinghardware 23 with high speed transport interface through electricallyconnecting with the CPU bus 13, the pin holes of the second CPU socket12, the pin grid array 21 of the mezzanine card 20, and the chip socket22 of the mezzanine card 20 in sequence (Step S30). Finally, themotherboard 10 is booted and activated. The motherboard 10 will detectthe expanding hardware 23 in the mezzanine card 20 during the bootingprocedure. The detected expanding hardware 23 will be registered in thesystem hardware resource. In addition, the motherboard 10 set the CPUbus 13 as a data transmission path for the expanding hardware 23 (StepS40).

Therefore, the present invention can be applied to a motherboard withplural CPU structure. Especially, when a CPU chip is used in amotherboard with dual CPU socket, the other CPU socket will be idle. Atthis time, the idled CPU socket can be utilized to provide an additionaltransport interface by the mezzanine card of the present invention, sothat the expanding hardware can be electrically connected to the CPUchip and controlled by the CPU chip. Therefore, the CPU chip can alsogenerate an expanding effect by the method of the present invention, andthe space in a notebook can be fully utilized.

In the above embodiment, the first CPU socket 11 is a first order of CPUsocket for the motherboard 10. In the other words, the first socket 11is a main CPU socket and the second socket 12 is a sub CPU socket.

While the preferred embodiments of the invention have been described, itwill be apparent to those skilled in the art that various modificationsmay be made without departing from the spirit of the present invention.Such modifications are all within the scope of the present invention.

1. An expanding high speed transport interface hardware method formotherboard, applied to a motherboard having a plural CPU structure, aCPU bus with high speed transport interface being used to connect afirst CPU socket and a second CPU socket of the motherboard, the methodcomprising steps of: providing a mezzanine card having a pin grid arraydisposed on a bottom surface of the mezzanine card, number of contactpins of the pin grid array being less then that of pin holes of thesecond CPU socket, and a top surface of the mezzanine card having a chipsocket with a high speed transport interface being electricallyconnected with the pin grid array; installing an expanding hardware withhigh speed transport interface in the chip socket; inserting themezzanine card into the idle second CPU socket, to make the pin gridarray to electrically connect with the pin holes of the second CPUsocket, so that the pin holes of the first CPU socket can beelectrically connected with the expanding hardware with high speedtransport interface through electrically connecting with the CPU bus,the second CPU socket, the pin grid array, and the chip socket; andactivating the motherboard, the motherboard detecting the mezzanine cardand the expanding hardware and setting the CPU bus as a datatransmission path between the mezzanine card and the expanding hardware.2. The expanding high speed transport interface hardware method formotherboard as claimed in claim 1, wherein the high speed transportinterface includes a hyper transport bus interface.
 3. The expandinghigh speed transport interface hardware method for motherboard asclaimed in claim 1, wherein the first CPU socket is a first order of CPUsocket for the motherboard.
 4. The expanding high speed transportinterface hardware method for motherboard as claimed in claim 1, whereinthe second CPU socket is a first order of CPU socket for themotherboard.
 5. The expanding high speed transport interface hardwaremethod for motherboard as claimed in claim 1, wherein signalspecification of the chip socket and signal specification of thecorresponding pin holes of the second CPU socket are same to each other.6. The expanding high speed transport interface hardware method formotherboard as claimed in claim 2, wherein hyper transport bus interfaceincludes a bridge chipset.
 7. The expanding high speed transportinterface hardware method for motherboard as claimed in claim 6, whereinthe bridge chip includes an 8131 chipset.